The present invention is related to cache memories and, more particularly, to high-speed synchronous external cache memory subsystems.
High performance processor systems generally include an external cache memory to improve the system""s performance. In many of the highest performance processor systems currently available, the external cache is implemented with high speed synchronous static random access memories (SRAMs). These conventional high performance processor systems typically use SRAMs having either a pipelined architecture or having a flow-through access architecture.
In general, pipelined architecture SRAMs are faster than flow-through architecture SRAMs. However, pipelined architecture SRAMs typically are smaller (i.e., in memory size) and more expensive than flow-through type SRAMs. Moreover, pipelined architecture SRAMs capable of operating at the same rate expected for the next generation of processors (e.g., at clock rates of over 200 MHz) are expected to be especially expensive. Consequently, processor designers can trade-off speed for cost and memory size by designing the processor to support operation with either pipelined architecture SRAMs or flow-through architecture SRAMs. The applicants are not aware of any processor systems that support operation in both modes.
In addition, as processor and SRAM technology improves, increases in clock rate for synchronous SRAMs are expected to lag behind the increases in clock rate for processors. As a result, when a new generation of processors is released, SRAMs capable of operating at the processor""s clock rate may not yet be available. Accordingly, as processor clock rates increase, there is a need for these processors to be capable of having optimal performance with both SRAMs that can and cannot operate at the same clock rate as the processor.
In accordance with the present invention, a cache memory subsystem includes an external synchronous RAM, a processor and a cache control unit. The external synchronous RAM the processor, and the cache control unit all interact with each other as the processor accesses the cache memory. In one embodiment, the cache control unit is built into the processor and the synchronous RAM is a SRAM that serves as the external cache memory. The cache control unit provides appropriately timed control signals to the SRAM when the processor is accessing the cache memory. The SRAM can be either a pipelined architecture SRAM (register output SRAM) or a flow-through access architecture SRAM (Catch output SRAM). The cache control unit is selectably configured to operate in either a pipelined mode (1-1-1) when the SRAM is a register output SRAM, or a flow-through (2-2) mode when the SRAM is a latch output SRAM. Pipelined architecture SRAMs having a clock rate equal to the processor can be operated in the 1-1-1 mode, which has a lower latency than the 2-2 mode. In accordance with the present invention, SRAMs that cannot be clocked at the same rate as the processor are then accessed in the 2-2 mode at a clock rate that is half of the processor clock rate. The 2-2 mode has a lower latency than simply clocking a pipelined architecture SRAM at half the processor clock rate, as is done in some conventional cache subsystems. Accordingly, a cache subsystem according to the present invention has better performance than these conventional subsystems when using relatively slow SRAMs.